The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a semiconductor structure including at least one high dielectric constant (k)/metal gate stack having self-aligned contacts and a method of fabricating such a structure.
As semiconductor devices shrink in each generation of semiconductor technology, formation of contact structures to source and drain regions of a field effect transistor become challenging because such contact structures not only need to provide reliable electrical contact to the source and drain regions, but also need to avoid electrically shorting to other components such as the gate electrode of the field effect transistor. Since the etch chemistry employed for the anisotropic etch process remains the same while the lateral dimension of the dielectric gate spacer shrinks with the scaling of semiconductor devices, the likelihood of overlay variations during lithographic processes causing formation of contact structures that electrically short a source/drain region to a gate conductor of a field effect transistor increases in each generation.
Nonetheless, contact structures to source and drain regions must avoid electrically shorting to gate conductors to provide a functional field effect transistor. Thus, the possibility of electrically shorting source/drain regions to a gate conductor of a field effect transistor is a significant concern for product yield and reliability purposes.